In general, a ROM (Read Only Memory), utilized for writing various pieces of program information, has a MOS (Metal Oxide Semiconductor) transistor construction having a gate, a source and a drain combined in a matrix format, that is, a construction which has laminated metal, oxide (insulator) and semiconductors, and which cuts off or connects the source and the drain of the memory-use transistor, or sets two types of threshold values, in accordance with written information, so that it detects a current flowing between the drain and the source in a manner so as to correspond to "1" and "0" in stored information.
For example, as shown in FIGS. 7(a) and 7(b), such a conventional mask ROM of an NOR type with high integrity includes a P-type semiconductor (Si) substrate 51, N-type semiconductor areas 57, and gate electrodes 59. Here, the N-type semiconductor areas 57, formed into a plurality of stripes in one direction, are formed on an upper portion of the P-type semiconductor substrate 51, and the gate electrodes 59, formed into a plurality of stripes that extend perpendicular to these N-type semiconductor areas 57 through a gate oxidation film 58, are also installed on the upper portion of the P-type semiconductor substrate 51. Memory cells are placed at intersections between the N-type semiconductor areas 57 and the gate electrodes 59.
Source areas and drain areas, made of the adjacent N-type semiconductor areas 57, are located below the respective gate electrodes 59, and operation channels 54 are formed between the source areas and the drain areas. In the case when the threshold voltage of each operation channel 54 is preliminarily set to a predetermined value for each portion, upon application of a voltage not less than the predetermined value to the gate electrodes 59 through word lines A1, A2 . . . , the operation channels 54 are allowed to conduct, and electrons are allowed to shift from the source side toward the drain side (in this case, bit lines f1, f2 . . . , have been preliminarily set so as to satisfy drain voltage&gt;source voltage); thus, a drain current is allowed to flow. Consequently, the writing process for information "1" is carried out.
In other words, when a positive voltage is applied to the gate electrodes 59, in the operation channel 54, a positive hole of the P-type semiconductor substrate 51 is pushed inward, and in contrast, a negative charge that is an electron is induced. When the positive voltage of the gate electrodes 59 increases, the number of electrons in the operation channel 54 increases, with the result that an N-type transmitting layer is formed, and this allows the source area and the drain area that have the same N-type to conduct, thereby allowing a current to flow. Here, these transistors that form the N-type transmitting layer as the operation channel 54 are referred to as N-channel transistors. In contrast, those transistors that form the P-type transmitting layer as the operation channel 54 are referred to as P-channel transistors.
Here, in the case when boron (B) ions, which form an impurity to Si, are injected into the operation channel 54, since B is trivalent while Si is tetravalent, in this boron (B) ion injected area 55, there is a lack of one electron in order to form a covalent bond with an Si atom. Here, an attempt is made to compensate for the lack of one electron by gaining one electron from an adjacent Si atom so as to complete the covalent bond. As a result, a positive hole is formed at the original Si position.
When the concentration of boron (B) ions in the operation channel 54 is made high, the number of positive holes increases, with the result that even upon application of a predetermined positive voltage to the gate electrode 59 as described above, there is no increase in the number of electrons. This makes it possible to write information "0".
In other words, in the mask ROM, data is fixed at the time of manufacturing a device. Therefore, as described above, when an attempt is made to write "0" upon application of a predetermined voltage, boron (B) ions are preliminarily injected into the operation channel 54 at a high concentration at the time of the manufacturing process thereof.
However, in the above-mentioned semiconductor device, as illustrated in FIG. 7(a), the mask ROM of the NOR type needs 2F in the lateral direction pitch X per bit, and also needs 2F in the longitudinal direction pitch Y per bit, in the case of design rule F. For this reason, the area of the mask ROM of the NOR type occupies 4F.sup.2 per bit, raising problems in achieving a small-size, highly integrated device.
Here, F in the above-mentioned design rule F refers to a dimension, for example, given as F=0.25 .mu.m.